SYLLABUS
Course ID CE 301
Course Name Logic
Design
Semester Fall, 2008
Instructor Prof.
Dr. Mehmet E. DALKILIÇ
ANOUNCEMENT:
1^{st} Midterm on Saturday November 15^{th}
2008 09:0011:00 at C202 – C205
An A4 help sheet is allowed
(handwritten and no photocopy).
2^{nd }Midterm on Saturday December 20^{th}
2008 09:0011:00 at C501 – C504
An A4 help sheet is allowed
(handwritten and no photocopy).
Figure for Question6
Final Exam on Jan 22^{nd}
2009 11:0014:00 at M202205
Two third or more of the questions
will be from subjects after 2^{nd} midterm.
Three A4 help sheets are allowed (handwritten and no
photocopy). Help sheets may contain definitions, equations, examples from
lecture notes but must not contain problem solutions. Your help sheets will be
collected and controlled.
Good luck to you all.
ANNOUCEMENT ON
PARTICIPATION GRADES:
Each student should send
an email to mehmet.emin.dalkilic@ege.edu.tr
about his/her participation grade. Each message should clearly explain that
student’s class participation (attendance, motivation, contribution to class
activities/discussions and other aspects that is related to CE301 class) and
should clearly state a grade 1 to 10 scale. Note that sending this message is
itself an act of participation.
EMail mehmet.emin.dalkilic@ege.edu.tr
Class Times Wednesday
08:30 – 11:20 (section 1)
13:30 – 16:20 (section 2)
Office Hours TBA
Course
Objectives This course introduces students to the basic
building blocks of digital systems as well as logic design techniquies.
The objective of the course is to provide the basic knowledge to understand the
design and analysis of combinational and
sequential logic circuits, finite state machines, Programmable Logic Circuits
and the basic design blocks of digital computers.
COURSE OUTLINE
Week
# 
Chapter
# 
Topic 
1 
1 
Digital Systems and Information 
2 
2 
Combinational Logic: Circuits 
3 
2 
Combinational Logic: Optimization 
4 
3 
Combinational Logic: Design 
5 
Midterm I 

6 
3 
Combinational Logic: Functions 
7 
4 
Aritmetic Functions 
8 
5 
Sequential Circuits: Models 
9 
5 
Sequential Circuits: Design 
10 
Midterm II 

11 
5 
State Machine Design 
12 
6 
Programmable Logic 
13 
7 
Registers and Register Transfers 
14 
9 
Computer Design Basics 
15 
Final Review 
Textbook Mano,M.M, Kime, C. Logic and
Computer Design Fundamentals, 4/E, Prentice Hall, 2008
(http://www.writphotec.com/mano4/)
Course Web Page http://www.ube.ege.edu.tr/~dalkilic/ce301.html
Evaluation Quizzes : 20 %
Midterm
I : 20 %
Midterm
II :
20 %
Final : 30 %
Participation
: 10 %
Attendance Attendance in class is required at all times.
Students are expected to be fully prepared to discuss textbook readings and
course assignments.
Announcements
The students are expected to check their
emails and the web site of the course for the announcements.
Homework #1
(Do not submit. Your work will be evaluated through in class (first
hour) Quiz #1 on Oct. 22^{th} 2008)
1. Study all starred (*) problems at the Problems section of Chapter 1.
Note that * indicates that a solution is available on the Website of the
textbook.
2. Problems 1.6, 1.8, 1.12, 1.15
Homework #2
(Do not submit. Your work will be evaluated through in class (first
hour) Quiz #2 on Nov. 5^{th} 2008)
1. Problems with solutions on the book’s website: 2.1, 2.2, 2.7, 2.9, 2.10,
2.12
2. Problems 2.6, 2.8, 2.11, 2.13
Homework #3 (Do not submit. Your work will be evaluated through in class (first hour) Quiz #3 on
Nov. 12^{th} 2008)
Problems 2.13, 2.14, 2.16,
2.19, 2.20, 2.22, 2.24, 2.25
Homework #4 (Do not submit. Your work will be evaluated through in class (first hour) Quiz #4 on
Nov. 26^{th} 2008)
Problems 3.1, 3.2*, 3.3, 3.4,
3.6, 3.8, 3.10, 3.16, 3.24*, 3.29, 3.30*, 3.31
Homework #5
(Submit your homework on December 17^{th}
2008, first class hour)
Problems 4.5, 4.8, 4.10, 4.16
Homework #6 (Do not submit. Your work will be evaluated through in class (first hour) Quiz #6 on
Jan. 7^{th} 2009)
Problems 5.4, 5.6, 5.7*, 5.8,
5.10, 5.11*, 5.13*, 5.15
Homework #7 Study SR, D, T and JK Flip Flops and
related problems and lecture notes/examples in Chapter 5.
You will be asked to draw the
FlipFlop output waveforms given input waveforms in Quiz #7 on Jan. 14^{th}
2009.
Quiz solutions for morning and afternoon sections.
Lecture Slides Allce301lSlides
Alternative link to AllSiledes