UBI 601 Advanced Computer Architecture

 

 

Fall 2018

 

Instructor: Asst. Prof. Dr. İlker Kocabaş (ilker.kocabas@ege.edu.tr)

Assistant:

Time: Monday 09:30 – 12:00

Office Hour: Wednesday 15:00 – 17:00. For other times please make an appointment.

 

All important information about the course is available from this Web page.

 

 

Announcements:

*    Assignment-1 can be reached from here. (Submission deadline: 17.10.2018)

*    The assignments grades can be reached from here.

*    The final exam will take place on Monday, January 14, 2019 at 09:30 in the library of UBE.

 

 

Course Description:

Basic principles of computer architecture. Design and organization of computer architecture. Running of programs written with high level languages on computer hardware. Using of SPIM simulator. Interrupts, ISA and performance metrics. Single cycle data path, pipeline, pipelined data path and forwarding. Pipeline stallings and Intel Asm. SSE, MMX, caches, virtual memories, parallel programs and OpenMP. I/O, shared memories ve instruction level parallelism. Scheduling.

 

Goals:

Aim of this course is to comprehend how programs written with high level language works on computer hardware, to comprehend computer organization and performance analysis, to comprehend state of the art developments about computer architecture.

 

Prerequisites:

There are no course prerequisites.

 

Course Material:

*    Required lecture slides (available on the course’s web  page)

*    Textbooks:

*  1. Hannessy,  J. L. , Patterson, D. A., Computer Architecture: A Quantitative Approach, 3rd edition, Morgan Kaufman Pub. Inc., 1996.

*  2. Patterson,  D. A., Hennessy,  J. L., Computer Organization and Design, The Hardware/Software Interface, 3rd edition, The Morgan Kaufmann Series, 2007.

 

 

Tentative Course Syllabus:

Week

Topics

Supplementary Notes

1

Introduction

 

2

Instructions & Functions

Assignment#1

3

Interrupts, ISA and Performance

 

4

Single Cycle Data Path & Pipeline

 

5

Pipelined Data Path and Forwarding

 

6

Pipeline Stallings and Intel Asm

 

7

SSE, MMX and Caches

 

8

MIDTERM

 

9

Caches (Cont.), Cash-aware Programs, Cash Performance

 

10

Virtual Memory, Parallel Programs and OpenMP

 

11

IO and Shared Memory

 

12

Shared Memory (Cont.) and Instruction Level Parallelism

 

13

Scheduling

 

14

Project Representations

 

 

Grading (Tentative):

*    Assignments & Project 30%

*    Midterm 30%

*    Final 40%